The present invention is generally related to guided-wave interconnections and, more particularly, is related to guided-wave interconnections within a microelectronic package.
High performance microprocessors with heat sink capabilities will likely be required to dissipate hundreds of watts from sub-volt power supplies in near and long-term microelectronic technology generations. A need exists for low cost and high pin count microelectronic package technology that can satisfy power supply and heat removal requirements within such chips.
The mechanical performance of a microelectronic package is important for wafer-level testing, protection, and reliability. Wafer-level testing requires simultaneous reliable contact to all die across a non-planar wafer surface. In-plane (i. e., x-y axis) compliance is generally required to account for thermal expansion between the chip and printed wiring board (or other attachment substrate). Wafer-level testing and burn-in demands significant out-of-plane (i.e., z-axis) compliance in order to establish reliable electrical contact between wafer-level pads and test-card or printed wiring board probes due to the non-planarity of each surface.
Unlike conventional packaging, wafer-level packaging (WLP) is a continuation of integrated circuit manufacturing. In WLP, additional masking steps can be used after fabricating die pads to simultaneously package all die across a wafer. A unique class of WLP is called xe2x80x9ccompliant wafer-level packagingxe2x80x9d (CWLP). In CWLP, additional masking steps can be used after fabricating die pads to batch fabricate compliant x-y-z axis I/O leads between the die pads and the board pads. The use of compliant leads allows for the elimination of underfill between chip and substrate, and hence improves manufacturability and cost. A mechanically x-y-z flexible lead is formed between the die pad and the bump interconnection that would be joined with the board. Accordingly, there is a need in the industry for x-y-z compliant leads that provide high density, high electrical performance, low cost, and ability of batch fabrication.
Thus, a heretofore unaddressed need exists in the microelectronics industry to address the aforementioned deficiencies and/or inadequacies.
Briefly described, the present invention provides for chip-level electronic packages. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative wafer-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core.
The present invention also involves a method of fabricating chip-level electronic packages. A representative method includes the following steps: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
Other systems, methods, features, and advantages of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims.